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TMC22071A
Genlocking Video Digitizer
Features
* * * * * * * * * * * Fully integrated acquisition 3-channel video input multiplexer Two-stage video clamp Automatic gain adjustment Sync detection and separation Pixel and subpixel adjustment of HSYNC-to-Video timing Genlock to NTSC or PAL inputs Clock generation 8-bit video A/D converter Microprocessor interface Line-locked pixel rates - 12.27 MHz NTSC - 13.5 MHz NTSC or PAL Direct interface to TMC22x9x encoders Built-in circuitry for crystal oscillator No tuning or external voltage reference required 68 Lead PLCC or 100 Lead MQFP package
Description
The TMC22071A Genlocking Video Digitizer converts standard baseband composite NTSC or PAL video into 8-bit digital composite video data. It extracts horizontal and vertical sync signals and generates a pixel clock for the on-board 8-bit A/D converter and a 2x clock for the transfer of data to subsequent video processing decoding or encoding with the TMC22x5y Video Decoder or TMC22x9x Digital Video Encoder family. It also measures the color subcarrier phase and frequency and provides this data to the Encoder (for genlocked color NTSC or PAL encoding), or a frame buffer (for frame capture) over the digital composite video port. The TMC22071A includes a three-channel video input multiplexer, analog clamp, variable gain amplifier, and digital back porch clamp. The on-board oscillator circuitry generates the clock from a 20 MHz crystal or the clock source may be an external oscillator. It is programmable over a microprocessor interface for NTSC or PAL operation. No external component changes and no production tuning or service adjustments are ever required. The TMC22071A is fabricated in an advanced CMOS process, and is packaged in a 68 Lead PLCC or 100 Lead MQFP. Its performance is guaranteed from 0C to 70C.
* * * *
Applications
* Frame grabber * Digital VCR/VTR * Desktop video
Block Diagram
BACK PORCH CLAMP VIN1 MUX VIN2 VIN3 D/A LOWPASS FILTER ANALOG CLAMP GAIN A/D SUBCARRIER PHASE-LOCKED LOOP DATA SELECTOR CVBS7-0
SYNC SEPARATOR
GVSYNC GHSYNC
D/A CONTROL +1.2V DIRECT DIGITAL SYNTHESIZER HORIZONTAL PHASE-LOCKED LOOP PXCK LDV VALID
PFD IN
CLK IN
RT
EXT PXCK
COMP VREF
A0 CS R/W INT
PXCK SEL
CLK OUT
RESET D0
DDS OUT
RB
CBYP
65-22071-01
MICROPROCESSOR INTERFACE
ANALOG INTERFACE
DDS/PIXEL CLOCK INTERFACE
Rev. 1.0.5
TMC22071A
PRODUCT SPECIFICATION
Functional Description
The TMC22071A is a fully-integrated genlocking video A/D converter which digitizes NTSC or PAL baseband composite video under program control. It accepts video on three selectable input channels, adjusts gain, clamps to the back porch, and digitizes the video at a multiple of the horizontal line frequency. It extracts horizontal and vertical sync, measures the subcarrier frequency and phase (relative to the sampling clock), and provides the data along with digital composite video data over an 8-bit digital video port. Two sync outputs (GHSYNC and GVSYNC) are also provided. It generates 1x (LDV) and 2x (PXCK) pixel clocks for data transfer. PXCK also serves as a master clock for the companion TMC22x9x Encoders and TMC22x5y decoders. Operating parameters are set up via a serial microprocessor port. Internal or external voltage reference operation is available
amplitudes during initial genlock acquisition, and then (optionally) holds the gain constant. This results in a stable picture under variable signal conditions. Improperly terminated or weak video signals are handled in the TMC22071A by a selectable gain of +1.0 or +1.5. The higher gain can amplify a doubly-terminated signal which is reduced in amplitude by 2/3. If the input signal levels are well controlled, the automatic gain adjustment can be disabled and the gain held at its nominal value (unity or 1.5X).
Analog-to-Digital Converter
The TMC22071A contains a high-performance 8-bit A/D converter. Its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. The reference voltages to the A/D converter are set up by internal D/A converters under automatic control during genlock acquisition. These voltages determine the gain and offset of the A/D converter with respect to the video level presented at its input.
Timing
The TMC22071A operates from an internally-synthesized clock, PXCK, which runs at twice the pixel data rate. The nominal pixel rates may be set to 12.27 Mpps for NTSC and 13.5 Mpps for NTSC and PAL. Customers requiring 14.75 or 15 Mpps PAL operation should consult factory.
Low-Pass Filter
The digitized composite video stream is digitally low-pass filtered to remove chrominance components from the sync separator. Filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking portion of the video, improving the accuracy of the back porch blanking level detector. A digital sync separator provides the output sync signals, GHSYNC and GVSYNC, and times internal operations.
Video Input
Three high-impedance video inputs are selected by an internal multiplexer under host processor control. The device accepts industry-standard video levels of 1.23 Volts (sync tip to peak color = 1 volt sync tip to reference white). Good channel-to-channel isolation allows active video on all three inputs simultaneously. Antialiasing filtering (if used) and line termination resistors must be provided externally. The input selection is controlled by two bits in the Control Register.
Horizontal Phase-Locked Loop
A phase-locked loop generates PXCK, at twice the pixel rate. The reference signal for the horizontal phase-locked loop is generated by the Direct Digital Synthesizer (DDS). The DDS output is constructed with an internal D/A converter and is output from the TMC22071A via the DDS OUT pin. This signal is passed through an external LC filter and input to the horizontal phase-comparator. The frequency of the DDS output is one ninth of that of PXCK. A 20 MHz clock is required to drive the DDS. Preferably, this may be input to the TMC22071A via CMOS levels on the CLK IN pin. Alternately, a 20 MHz crystal may be directly connected between CLK IN and CLK OUT with tuning capacitors to activate the internal crystal oscillator circuitry. If incoming video is lost or disconnected after the TMC22071A has acquired and locked, PXCK, GHSYNC,
Analog Clamp
The front-end analog clamp ensures that the input video falls within the active range of the A/D converter. The digitized composite video output can be clamped to the back porch by a secondary digital clamp.
Automatic Gain Adjustment
Since video signals may vary substantially from nominal levels, the TMC22071A performs an automatic level setting routine to establish correct signal amplitudes for digitizing. The TMC22071A relies upon the presence of the sync tip-to-back porch voltage to determine the gain required for the input video signal. Sync tip compression or clipping is often affected by APL (Average Picture Level) variation. Rather than tracking minor variations in sync tip amplitude and constantly adjusting video gain, the TMC22071A establishes proper signal
2
PRODUCT SPECIFICATION
TMC22071A
GVSYNC and GRS data will continue. The GRS data will be the initial subcarrier frequency and phase values selected by the Format select bits of the Control Register. The TMC22071A will acquire and lock to incoming video within two frames after video is restored.
Subcarrier frequency, subcarrier phase, and Field ID data (GRS) are transmitted in 4-bit nibbles over CVBS3-0 during the horizontal sync tip period at the PXCK rate.
Microprocessor Interface
Since microprocessor buses are notoriously noisy from a wide-band analog point of view, the microprocessor interface bus is only one bit wide, rather than the more customary eight. The operation of this bus is similar to other buscontrolled devices except that the TMC22071A internal Control Register is accessed one bit at a time. A sequence of 47 bits is written to or read from the LSB of a standard microprocessor port. Writing to or reading from the secondary address results in the transfer of data to or from the internal shift register. The RESET input, when LOW, sets all internal state machines to their initialized conditions. Returning the RESET pin HIGH starts the signal acquisition sequence which lasts until locking with the gain-adjusted and clamped video signal is achieved.
Subcarrier Phase-Locked Loop
A fully-digital phase-locked loop is used to extract the phase and frequency of the incoming color burst. These frequency and phase values are output over the CVBS bus during the horizontal sync period. Fairchild's video decoder and genlockable encoder chips will accept these data directly.
Back Porch Digital Clamp
A digital back-porch clamp is employed to ensure a constant blanking level. It digitally offsets the data from the A/D converter to set the back porch level to precisely 3Ch for NTSC and 40h for PAL. When the digital clamp is enabled, the CVBS video output data is determined from the A/D conversion result minus the back porch level + 3Ch (40h for PAL).
Digitized Video Output
The digitized 8-bit video output is provided over an 8-bit wide CVBS data port, synchronous with PXCK and LDV.
Pin Assignments
1 68 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name VDD CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 VDD DGND CVBS5 CVBS6 CVBS7 GHSYNC GVSYNC VALID DGND DGND LDV Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name VDD PXCK DGND DGND VDD VDDA AGND VDDA VDDA AGND RB VIN3 VDDA VIN2 AGND VDDA VIN1 Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Name AGND RT AGND VREF AGND VDDA AGND CBYP PFD IN AGND DDS OUT PXCK SEL VDDA COMP AGND DGND CLK IN Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name VDD CLK OUT EXT PXCK DGND DGND DGND VDD VDD A0 R/W CS VDD RESET DGND D0 INT DGND
65-22071-02
3
TMC22071A
PRODUCT SPECIFICATION
Pin Assignments (continued)
80 81 51 50 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16* 17 18 19 20 21 22 23 24 25 Name A0 NC NC R/W CS VDD RESET DGND D0 NC NC NC NC NC NC DGND INT VDD NC NC CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41* 42* 43 44 45 46 47 48 49 50 Name VDD DGND CVBS5 CVBS6 CVBS7 NC GHSYNC GVSYNC VALID NC NC NC DGND DGND LDV DGND VDD NC VDD PXCK DGND DGND VDD VDDA AGND Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name VDDA VDDA NC NC AGND NC RB VIN3 NC VDDA VIN2 NC AGND VDDA VIN1 NC AGND RT AGND VREF NC AGND VDDA AGND CBYP Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name NC PFD IN NC NC NC AGND DDS OUT NC NC NC PXCK SEL VDDA COMP AGND DGND CLK IN VDD CLK OUT EXT PXCK DGND DGND DGND VDD NC VDD
65-22071-02B
100 1 30
31
Notes: 1. NC = Do Not Connect. * These pins are not connected in the TMC22071A. However, you should connect these pins as shown for compatibility with future genlock ICs.
Pin Definitions
Pin Number Pin Name Video Input VIN1-3 Clocks CLK IN 51 91 CMOS 20 MHz DDS clock input. 20 MHz CMOS clock input to DDS. This pin may also be used along with CLK OUT for directly connecting crystals. Inverted clock output. Inverted DDS clock output. This pin may also be used along with CLK IN for directly connecting a crystal. 2x Pixel clock output. 2x oversampled line-locked clock output. Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the rate of PXCK and its rising edge is useful for transferring CVBS digital video from the TMC22071A to the TMC22x9x Digital Video Encoders. External PXCK input. Input for external PXCK clock source. PXCK source select. Select input for internal or external PXCK. When HIGH, the internally generated line-locked PXCK is selected. When LOW, the external PXCK source is enabled. 34, 31, 29 65, 61, 58 1.23Vp-p Composite Video Input. Video inputs,1.25 Volts peak-to-peak, sync tip to peak color 68 pin PLCC 100 pin MQFP Pin Type Function
CLK OUT PXCK LDV
53 19 17
93 45 40
CMOS CMOS CMOS
EXT PXCK PXCK SEL
54 46
94 86
CMOS CMOS
4
TMC22071A
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin Number Pin Name GHSYNC 68 pin PLCC 12 100 pin MQFP 32 Pin Type CMOS Function Horizontal sync output. When the TMC22071A is locked to incoming video, the GHSYNC pin provides a negative-going pulse after the falling edge of the horizontal sync pulse. There is a fixed number of PXCK clock cycles between adjacent falling edges of GHSYNC, except following a VCR headswitch. Vertical sync output. When the TMC22071A is locked to incoming video, the GVSYNC pin provides a negative-going edge after the start of the first vertical sync pulse of a vertical blanking interval. Composite output bus. 8-bit composite video data is output on this bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier frequency, and subcarrier phase are available on this bus. Data l/O port. Microprocessor data port. All control parameters are loaded into and read back from the Control Register over this 1-bit bus. mP port control. Microprocessor address bus. A LOW on this input loads the l/O Port Shift Register with data from D0 and CS. A HIGH transfers the l/O Port Shift Register contents into the Control Register on the last falling edge of CS. Chip select. When CS is HIGH, D0 is in a high-impedance state and ignored. When CS is LOW, the microprocessor can read or write D0 data into the Control Register. Master reset input. Bringing RESET LOW forces the internal state machines to their starting states, loads the Control Register with default values, and disables outputs. Bringing RESET HIGH restarts the TMC22071A in its default mode. Bus read/write control. When R/W and A0 are LOW, the microprocessor can write to the Control Register over D0. When R/W is HIGH and A0 is LOW, the contents of the Status Register are read over D0. Interrupt output. This output is LOW if the internal horizontal phase lock loop is unlocked with respect to incoming video for 128 or more lines per field. After lock is established, INT goes HIGH. HSYNC locked flag. This output, when HIGH indicates that incoming horizontal sync has been detected within the 16 pixel window in time established by previous sync pulses. When LOW, it indicates that incoming horizontal sync has not been found within the expected time frame. VALID will toggle if the time stability of incoming video is such that sync positioning varies more than 16 pixels or if occasional horizontal sync pulses are missing.
Digital Video
GVSYNC
13
33
CMOS
CVBS7-0
11-9, 62
30-28, 25-21
CMOS
mP l/O D0 66 9 TTL
A0
60
1
TTL
CS
62
5
TTL
RESET
64
7
TTL
R/W
61
4
TTL
INT
67
17
TTL
VALID
14
34
TTL
5
PRODUCT SPECIFICATION
TMC22071A
Pin Definitions (continued)
Pin Number Pin Name VREF 68 pin PLCC 38 100 pin MQFP 70 Pin Type +1.23 V Function VREF input/output. +1.23 Volt reference. When the internal voltage reference is used, this pin should be decoupled to AGND with a 0.1 mF capacitor. An external +1.2 Volt reference may be connected here, overriding the internal reference source. Compensation capacitor. Compensation for DDS D/A converter circuitry. This pin should be decoupled to VDDA with a 0.1 mF capacitor. A/D VREF decoupling. Decoupling points for A/D converter voltage references. These pins should be decoupled to AGND with a 0.1 mF capacitor. Internal DDS output. Analog output from the internal Direct Digital Synthesizer D/A converter, at 1/9 the PXCK frequency. Horizontal PLL input. Analog input to the Phase/Frequency Detector of the horizontal phase-locked loop. 1 mF Comparator bypass. Decoupling point for the internal comparator reference of the Phase/Frequency Detector. This pin should be decoupled to AGND with a 0.1 mF capacitor. Analog power supply. Positive power supply to analog section.
Analog Interface
COMP
48
88
0.1 mF
RT,RB
36, 28
68
0.1 mF
PLL Filter DDS OUT PFD IN CBYP 45 43 42 82 77 75
Power Supply VDDA 23, 25, 26, 30, 33, 40, 47 49, 51, 52, 60, 64, 73, 87 +5 V
VDD
1, 7,18, 6, 18, 22, 52, 26, 42, 58,59,63 44, 48, 92, 98, 100 24, 27, 32, 35, 37, 39, 41, 44, 49, 8, 15, 16, 20, 21, 50, 55-57, 65, 68 50, 55, 63, 67, 69, 72, 74, 81, 89 8, 16, 27, 38, 39, 41, 46, 47, 90, 9597
+5 V
Digital power supply. Positive power supply to digital section.
Ground AGND 0.0 V Analog ground. Ground for analog section.
DGND
0.0 V
Digital ground. Ground for digital section.
6
PRODUCT SPECIFICATION
TMC22071A
Control and Status Registers
The TMC22071A is controlled by a single 47-bit long Control Register. Access to the Control Register is via the I/O Port Shift Register arranged as shown in Figure 1. The Control Register can be written, with the desired programming. The 12-bit Status Register is read-only and accessed through the same l/O Port Shift Register. Reading the Status Register yields information about blanking level, subcarrier presence, and whether or not PXCK is locked or unlocked with respect to the line rate.
Table 1. Microprocessor Port Control
A0 0 0 1 1 R/W 0 1 0 1 Action Write data from D0 into l/O Port Shift Register Read D0 data from last stage of l/O Port Shift Register Transfer l/O Port Shift Register contents to Control Register Enables continuous update of status bits in l/O Port Shift Register
D0
I/O Port Shift Register
0 Control Register
46
47 58 Status Register
65-22071-03
The full sequence of 47 bits of Control Register data must be written each time a change in that data is desired. All or a few of the Control and Status Register bits may be read, but the sequence always begins with bit 58 of the Status Register.
CS
Figure 1. Control and Shift Register Structure
R/W
The host processor writes data into the TMC22071A using only one bit of the microprocessor's data and address bus. As shown in Figure 2, the user should bring A0 high for the CS falling edge preceding the introduction of bit 0 to the D0 port. The next rising edge of CS completes the preloading of the control data, which transfer into the control register on the next rising edge of the pixel clock. The I/O Port Shift Register, Control Register and Status Register are governed by CS, R/W, and A0. R/W and A0 are latched by the TMC22071A on the falling edge of CS and data input D0 is latched on the rising edge of CS. Data read from D0 is enabled by the falling edge of CS and disabled by the rising edge of CS. When the Control Register is read more than once consecutively, an extra CS pulse and accompanying A0 is needed to align the circulated shift register data.
D0 A0
46
45
1
0 tH tS
65-22071-04
Figure 2. Data Write Sequence
CS
R/W
D0 A0
58
57
1
0
65-22071A-05
Figure 3. Data Read Sequence
7
TMC22071A
PRODUCT SPECIFICATION
0 000 SRESET FORMAT
7
8 00 VGAIN SOURCE TEST SUBPIX
15 16
23
TEST
(LSB)
24 0001 LEADLAG AGC FREERUN
31 32
39 40 00000 00
LEADLAG
46
STATUS REGISTER 47 54 55 58
COLOR (LSB)
LOCK
BLKAMP
(MSB)
TEST TEST
Figure 4. Control Register Map
Control Register Bit Functions
Bit 0 Name SRESET Function Software reset. When LOW, resets and holds internal state machines, resets Control Register with previously written values, and disables output drivers. When HIGH, SRESET starts and runs state machines, PXCK, and enables outputs. Input signal format select. Bit 3 is the MSB. 000 NTSC at 12.27 Mpps. 001 NTSC at 13.5 Mpps. 010 Reserved. 011 Reserved. 100 PAL at 13.5 Mpps. 101 Reserved. 11x Reserved. 4-6 7,8 TEST SOURCE Factory test control bits. These should be set LOW. Video source select. Bit 8 is the MSB. 00 VIN1 01 VIN2 1x VIN3 9 10-11 12-16 VGAIN TEST SUBPIX Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X. Factory test control bits. These should be set LOW. These control bits allows the HSYNC, VSYNC, and sample clock to be time-shifted by -16/32 to +15/32 pixels. Bit 16 is the two's complement MSB. When SUBPIX is 00h, HSYNC and incoming video are subject to LEADLAG. A value of 18h delays HSYNC 1/4 pixel. A value of 08h advances HSYNC 1/4 pixel. This control word allows the HSYNC and VSYNC to be time-shifted -122 to +132 LDV cycles. When LEADLAG is 7Bh, HSYNC and incoming video are in alignment. A value of 83h delays HSYNC eight LDV cycles. A value of 73h advances HSYNC eight LDV cycles. Bit 24 is the MSB.
1-3
FORMAT
17-24
LEADLAG
8
TEST TEST GRSONLY
65-22071-06
TEST BPFOUT DCLAMP
VCR/TV CVBSEN
STVAL
TEST
TEST
PRODUCT SPECIFICATION
TMC22071A
Control Register Bit Functions (continued)
Bit 25 Name AGC Function AGC operation control. After H and V sync acquisition, the A/D converter references are adjusted to encompass the full video range. The system can initiate an A/D adjustment sequence at any time by bringing this bit HIGH. The control bit will reset to 0 following AGC adjustment. When HIGH, a free-running PXCK is generated, independent of incoming video. When LOW, PXCK is locked to incoming video. Factory test control bits. These should be set LOW. Block sync enable. When HIGH the TMC22071A accepts both normal and block sync. (In block sync, the incoming signal is at the sync tip level for 2.5 (PAL) or 3 (NTSC) consecutive lines. Equalization pulses may be absent.) When LOW, only normal sync may be input. For most applications, whether using a VCR or a studio video input source, best performance will be found when this bit is HIGH. CVBS bus enable. When LOW, the CVBS7-0, GHSYNC, and GVSYNC outputs are in a high-impedance state. When HIGH, they are enabled. Factory test control bit. This should be set LOW. Burst phase / frequency output control. When HIGH, GRS is disabled. When LOW, burst phase and frequency information is output on CVBS3-0. Digital clamp enable. The digital clamp is enabled when DCLAMP is HIGH and disabled when LOW. Factory test control bits. These should be set LOW. Sync tip value. When DCLAMP is HIGH and STVAL is set to its default value 3h the output sync level is 3h for NTSC and 7h for PAL. Bit 43 is the MSB. VCR lock control. Setting this bit LOW improves the TMC22071A's locking to VCR signals. When only clean video input signals are used, the user may set this bit HIGH for compatibility with existing TMC22071 firmware. Factory test control bit. This should be set LOW. When the horizontal phase lock loop becomes unlocked (i.e. after video input is disconnected) and this Control Bit is HIGH, all CVBS data is forced LOW except subcarrier frequency and phase data (GRS). GHSYNC, GVSYNC, and PXCK continue with default GRS data until video is required. The presence of GRS also depends upon bit 33. If the GRSONLY bit is LOW, GHSYNC, GVSYNC, and PXCK continue with default GRS data continue but video pixel data is random. Burst present status bit. This bit is HIGH when burst is present on the input video. It is LOW, when burst is not present. Blanking amplitude status bit. These eight bits report the actual blanking level. H-lock loop status bit. When HIGH, the TMC22071A is not locked to an input signal. When LOW, lock has been achieved. These are read-only bits for testing puposes only.
26 27-29 30
FRERUN TEST VCR/TV
31 32 33 34 35-39 40-43 44
CVBSEN TEST BPFOUT DCLAMP TEST STVAL VCR
45 46
TEST GRSONLY
Status Bits (Read Only) 47 48-55 56 57-58 COLOR BLKAMP LOCK TEST
9
TMC22071A
PRODUCT SPECIFICATION
Horizontal Timing
Horizontal line rate is selectable, and is determined by the FORMAT control bits (12.27 Mpps for NTSC, 13.5 Mpps for NTSC and PAL). Figure 5 illustrates the horizontal blanking interval. Figure 6 completes the definition of timing parameters with vertical blanking interval detail.
2.35 sec PAL 2.3 sec NTSC Equalizing Pulse Video In
H 0.5H 4.7 sec Serration
GVSYNC tVD GHSYNC (Odd Field) GHSYNC (Even Field) tDH
65-22071-08
Video In
Burst
Figure 6. Vertical Sync timing
Programming the TMC22071A
tDH GHSYNC
65-22071-07
Figure 5. Horizontal Sync Timing
Upon power-up after bringing RESET LOW, the TMC22071A Control Register is set to default values as shown in the top entry of Table 3. These default values do not necessarily render the TMC22071A operational in any specific application. Before the TMC22071A is expected to acquire input video, its Control Register must be loaded with data that is specific to its use.
Table 2.TMC22071A Timing Options
Standard NTSC NTSC-601 PAL-601 Field Rate (Hz) 59.94 59.94 50.00 Line Rate (kHz) 15.734264 15.734264 15.625 Pixel Rate (Mpps) 12.2727+ 13.50 13.50 PXCK Frequency (MHz) 24.54+ 27.0 27.0 Plxels Per Line 780 858 864
Table 3. Control Register Example Data
Control Register Data (Bit 56 ...... Bit 0) Standard DEFAULT NTSC NTSC-601 PAL-601 46 0000 0010 0010 0010 42 0110 0110 0110 1110 38 0000 0000 0000 0000 34 1001 1001 1001 1001 30 0000 1000 1000 1000 26 0010 0010 0010 0010 22 0000 0000 0000 0000 18 0000 0000 0000 0000 14 0000 0000 0000 0000 10 0000 00xx 00xx 00xx 6 0000 0000 0000 0001 2 001 000 010 xx0
10
PRODUCT SPECIFICATION
TMC22071A
CVBS Bus Data Formats
The CVBS bus outputs a Genlock Reference Signal (GRS) along with the 8-bit digital composite video data. The range of output data versus video input voltage is illustrated in Figure 7 where sync tip and blanking levels are controlled by the digital backporch clamp of the TMC22071A. During horizontal sync, the TMC22071A outputs field identification, subcarrier frequency, and subcarrier phase information on the CVBS bus.
Peak Chrominance Peak Luminance NTSC PAL FEh D2h FFh CFh
Field identification is output on CVBS2-0. The LSB, CVBS0, will be LOW during odd fields and HIGH for even fields. When NTSC operation is selected, CVBS1-0 count 00,01,10,11 for fields 1 through 4 respectively. When PAL operation is selected, CVBS2-0 count 000, 001, 010, etc. to 111 for fields 1 through 8, respectively. CVBS3 indicates V-component inversion in PAL. It is HIGH for NTSC lines (burst 135) and LOW for PAL lines (burst 225) Subcarrier frequency is sent out in a 24-bit binary representation in six 4-bit nibbles on CVBS3-0. Subcarrier frequency data, f23-0, is identical to the pre-programmed BSEED value used in the TMC22071A to lock the subcarrier phase-locked loop to the incoming subcarrier frequency. Subcarrier phase, F23-0, is also sent out in a 24-bit binary representation in six 4-bit nibbles on CVBS3-0. Bit F23 is the MSB.
Back Porch Burst Sync Tip Blanking 3Ch 03h 40h 03h
65-22071-09
Figure 7. Output Data vs. Input Video Level
PXCK 0 GHSYNC 1 2 3 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
CVBS7:0
PIXEL
PIXEL
PIXEL
f23:20 f19:16 f15:12 f11:8
f7:4
f3:0
f23:20 f19:16 f15:12 f11:8
f7:4
f3:0
PIXEL
PIXEL
FREQUENCY FIELD IDENTIFICATION
PHASE
65-22071-10
Figure 8. Genlock Reference Signal (GRS) Format
tPWHPX PXCK tDO GHSYNC tXL LDV tHO CVBS7:0
tPWHPX
1/fPXCK
tXV
PIXEL 0
PIXEL 1
65-22071-11
Figure 9. CVBS Bus Video Data Format
11
TMC22071A
PRODUCT SPECIFICATION
tPWLCS CS tSA R/W tHA
tPWHCS
A0 tSD D0
65-22071-12
tHD
Figure 10. Microprocessor Port - Write Timing
tPWLCS CS tSA R/W tHA
tPWHCS
A0 tDOM D0 tDOZ
65-22071-13
tHOM
Figure 11. Microprocessor Port - Read Timing
12
PRODUCT SPECIFICATION
TMC22071A
Equivalent Circuits and Transition Levels
VDD n Substrate VDD
2k1/2 PFD IN CBYP +2.4 V + - p
VDD p
n VDD
p
DDS OUT 1501/2
65-22071-14
65-22071-15
Figure 12. Equivalent PFD IN Circuit
Figure 13. Equivalent DDS OUT Circuit
VDD n Substrate p
VDD
p
Input
Output
n
n
65-22071-16
65-22071-17
Figure 14. Equivalent Digital Input Circuit
Figure 15. Equivalent Digital Output Circuit
tDOM CS
tHOM
0.5 V
tDOZ
D0
Hi-Z
2.0 V 0.8 V
65-22071-18
0.5 V
Figure 16. Transition Levels for Three-State Measurements
13
TMC22071A
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Power Supply Voltage Input Voltage Digital Outputs Applied Voltage2 Forced Current Temperature Operating, Case Operating, Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -60 130 150 300 220 150 C C C C C
3,4
Min. -0.5 -0.5 -0.5 -6.0
Max. 7.0 VDD + 0.5 VDD + 0.5 6.0 1
Unit. V V V mA sec
Short Circuit Duration (single output in HIGH state to GND)
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
Operating Conditions (for standard temperature range)
Parameter VDD VIH Power Supply Voltage Input Voltage, Logic HIGH TTL Inputs CMOS Inputs VIL Input Voltage, Logic LOW TTL Inputs CMOS Inputs IOH lOL VIN VREF TA tPWHCS tPWHCS tSA tHA tSD tHD Output Current, Logic HIGH Output Current, Logic LOW Video Input Signal Level, Sync Tip to Peak White External Reference Voltage Ambient Temperature, Still Air CS Pulse Width, LOW CS Pulse Width, HIGH Address Setup Time Address Hold Time Data Setup Time Data Hold Time 0 16 20 0 0 50 50 1.0 1.235 70 DGND DGND 0.8 1/3 VDD -2.0 4.0 V V mA mA V V C ns ns ns ns ns ns 2.0 2/3VDD VDD VDD V V Min. 4.75 Nom. 5.0 Max. 5.25 Units V
Microprocessor Interface
Note: 1. Timing reference points are at the 50% level.
14
PRODUCT SPECIFICATION
TMC22071A
Electrical Characteristics (for standard temperature range)
Parameter IDD Power Supply Current
1
Conditions Total Current VDD = Max, fPXCK = 30MHz VREF = +1.235V VDD = Max, VIN = 4.0V VDD = Max, VIN = 0.4V IOH = -2.0 mA IOL = 4.0 mA VDD = Max, VIN = VDD VDD = Max, VIN =GND TA = 25C, f = 1 Mhz TA - 25C, f = 1 Mhz TA = 25C, f = 3.58 Mhz
Min
Typ 190
Max 230
Units mA
IREF IIH IIL VOH VOL IOZH IOZL Cl CO CV RV
Reference Inputcurrent Input Current, Logic HIGH Input Current, Logic LOW Output Voltage, Logic HIGH Output Voltage, Logic LOW Hi-Z Output Leakage current, HIGH Hi-Z Output Leakage current, LOW Digital Input Capacitance Digital Output Capacitance Input Capacitance, VIN1-3 Input Resistance, VIN1-3
100 10 10 2.4 0.4 10 10 4 10 15 50 15
mA mA mA V V mA mA pF pF pF kW
Note: 1. Typical IDD with VDD = +5.0 Volts and TA = 25C, Maximum IDD with VDD = +5.25 Volts and TA = 0C.
Switching Characteristics (for standard temperature range)
Parameter tDO tHO fPCK fPXCK tPWHPX tPWHPX tDH tVD tXL tXV tDOM tHOM tDOZ Output Delay Time Output Hold Time Pixel Rate Master Clock Rate PXCK Pulse Width, LOW PXCK Pulse Width, HIGH Horizontal Sync to GHSYNC Vertical Sync to GVSYNC PXCK LOW to LDV HIGH PXCK LOW to LDV LOW D0 enable time D0 disable time CS LOW to D0 output driven 10 20 15 5 Conditlons CLOAD = 35 pF Min 2 3 12 24 12 12 14 14 8 8 Typ Max 15 8 15.3 30.6 Units ns ns MHz MHz ns ns pixels pixels ns ns ns ns ns
15
TMC22071A
PRODUCT SPECIFICATION
System Performance Characterlstics
Parameter ESCH ESCP tAL VXT Sync time-base variation Subcarrier Phase Error1 Line-lock Acquisition Time Channel-to-Channel Crosstalk @3.58 Mhz
1
Min
Type
Max 3 2 2 -35
Units ns degrees frames dB
Note: 1. NTSC/PAL compliant black burst at nominal input level 10%, frequencies nominal 10 ppm.
+5V Ferrite Bead Digital Supply Plane 10F 0.1F DGND Video A Video B Video C
LPF
6.8 pF 10H 150 pF 390 pF 0.01 F +5V
Analog Supply Plane* 10F 0.1F AGND DDS OUT PFD IN COMP VREF 0.1F 3.3K1/2
VDD VDDA
3.3 F VIN1 751/2 3.3 F 3.3 F VIN3 751/2 EXT PXCK RESET D0 A0 CS R/W INT VALID VIN2
LPF
751/2
LPF
TMC22071A Genlocking Video Digitizer
LM385-1.2 RT 0.1F RB CVBS7:0 GHSYNC GVSYNC PXCK LDV 0.1F 8 DIGITAL VIDEO INTERFACE
0.1F
20 MHz, TTL
CLK IN CLK OUT PXCK SEL
CBYP 0.1F
and
must be connected
MICROPROCESSOR INTERFACE
65-22071A-19
via low-impedance path
*section of supply plane beneath analog interface circuitry
Figure 17. Typical Interface Circuit
Application Notes
The TMC22071A is a complex mixed-signal VLSI circuit. It produces CMOS digital signals at clock rates of up to 15 MHz while processing analog video inputs with a resolution of less than a few millivolts. To maximize performance it is important to provide an electrically quiet operating environment. The circuit shown in Figure 17 provides an optional external 1.2V reference to the VREF input of the TMC22071A. The internal VREF source is adequate for most applications.
Chebyshev response with-3dB bandwidth of 6.7MHz and a group delay of 140 nanoseconds at 5MHz. The filter of Figure 19 has been equalized for group delay in the video signal band. Its -3dB passband is 5.5MHz while the group delay is constant at 220 nanoseconds through the DC to 5MHz frequency band.
2.2H 2.2H
Flltering
Inexpensive low-pass anti-aliasing filters are shown in Figures 18 and 20. These filters would normally be inserted in the video signal path just before the 75W terminating resistor and AC-coupling capacitor for each of the three video inputs, VIN1-3. The filter of Figure 18 exhibits a 5th-order
470 pF
1000 pF
470 pF
65-22071-20
Figure 18. Simple Anti-aliasing Filter
16
PRODUCT SPECIFICATION 3.3 H 3.3 H 4.7 H 4.7 H
TMC22071A
Grounding
The TMC22071A has separate analog and digital circuits. To minimize digital crosstalk into the analog signals, the power supplies and ground connections are provided over separate pins (VDD and VDDA are digital and analog power supply pins; DGND and AGND are digital and analog ground pins). In general, the best results are obtained by tying all grounds to a solid, low-impedance ground plane. Power supply pins should be individually decoupled at the pin. Power supply noise isolation should be provided between analog and digital supplies via a ferrite bead inductor on the analog lead. Ultimately all +5 Volt power to the TMC22071A should come from the same power source. Another approach calls for separating analog and digital ground. While some systems may benefit from this strategy, analog and digital grounds must be kept within 0.1V of each other at all times.
430 pF
750 pF
430 pF
470 pF 2.2 H
470 pF 910 H
65-22071-21
Figure 19. Group Delay Equalizer Filter
Using a 20 MHz Crystal
In systems where a 20 MHz clock is not available, a crystal may be used to generate the clock to the TMC22071A. The crystal must be a 20 MHz "fundamental" type, not overtone. Specific crystal characteristics are listed in Table 4 and the connections are shown in Figure 20.
Table 4. Crystal Parameters
Parameter Fundamental frequency Tolerance Stability Load Capacitance Shunt Capacitance ESR 20 MHz 30 ppm @ 25C 50 ppm, 0C to 70C 20 pF 7 pF Max. 50 W, Max. Value
Interface to the TMC22x9x Encoder
The TMC22x9x Digital Video Encoders have been designed to directly interface to the TMC22071A Digital Video Genlock. The TMC22071A is the source for TMC22x9x input signals CVBS7-0, GHSYNC, GVSYNC, LDV, and PXCK as shown in Figure 21. These signals directly connect to the TMC22x9x. The microprocessor interface for TMC22x9x and TMC22071A are identical. All R/W, RESET, data and address bus signals from the host microprocessor are shared by the TMC22x9x and TMC22071A. Only CS, VALID, and INT signals are separate from the microprocessor bus.
TMC22071A 33 pF CLK IN 20 MHz Crystal 33 pF
65-22071A-22
1M1/2 3001/2 CLK OUT
Figure 20. Direct Crystal Connections
CVBS7:0 GHSYNC GVSYNC PXCK TMC22071A LDV GENLOCKING VIDEO DIGITIZER RESET D0
8
CVBS7:0 GHSYNC GVSYNC PXCK LDV
TMC22x9x DIGITAL VIDEO ENCODER RESET D7:0
A1:0
CS R/W
2
8
CS R/W
65-22071A-23
A0
MICROPROCESSOR INTERFACE
Figure 21. TMC22x9x Interface Circuit 17
TMC22071A
PRODUCT SPECIFICATION
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (COMP,VREF, RT, RB, DDS OUT, PFD IN, CBYP, and VIN1-3) as short as possible and as far as possible from all digital signals. The TMC22071A should be located near the board edge, close to the analog output connectors. The digital power plane for the TMC22071A should be that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the analog power supply for the TMC22071A is the same as that of the system's digital circuitry, power to the TMC22071A VDDA pins should be decoupled with ferrite beads and 0.1 mF capacitors to reduce noise. The ground plane should be solid, nor cross-hatched. Connections to the ground plane should have very short leads.
4.
Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They typically supply adjacent circuits on the device, which generate varying amounts of noise. For best results, use 0.1mF capacitors in parallel with 10mF capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. If the digital power supply has a dedicated power plane layer, it should not overlap the TMC22071A, the voltage reference or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC22071A and its related analog circuitry can degrade performance. CLK should be handled carefully. Jitter and noise on this clock or its ground reference may degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing.
5.
2.
6.
Related Products
* * * * * TMC22x9x Digital Video Encoders TMC2242/TMC2243/TMC2246 Video Filters TMC2081 Digital Video Mixer TMC22x5y Digital Decoders TMC2302 Image Manipulation Sequencer
3.
18
PRODUCT SPECIFICATION
TMC22071A
Notes:
19
TMC22071A
PRODUCT SPECIFICATION
Notes:
20
PRODUCT SPECIFICATION
TMC22071A
Notes:
21
TMC22071A
PRODUCT SPECIFICATION
Mechanical Dimensions
68 Lead PLCC Package
Inches Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
Symbol
.165 .200 .090 .130 .020 -- .013 .021 .026 .032 .985 .995 .950 .958 .800 BSC .050 BSC .042 17 68 -- .004 .056
4.19 5.08 2.29 3.30 .51 -- .33 .53 .66 .81 25.02 25.27 24.13 24.33 20.32 BSC 1.27 BSC 1.07 17 68 -- 0.10 1.42
3
2
E E1 J
D D1
D3/E3
e A
B1
J
A1 A2 B -CLEAD COPLANARITY ccc C
22
PRODUCT SPECIFICATION
TMC22071A
Mechanical Dimensions (continued)
100 Lead MQFP Package - 3.2mm Footprint
Symbol A A1 A2 B C D D1 E E1 e L N ND NE
a ccc
Inches Min. -- .010 .100 .008 .005 .904 Max. .134 -- .120 .015 .009 .923
Millimeters Min. -- .25 2.55 .22 .13 22.95 Max. 3.40 -- 3.05 .38 .23 23.45
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
3, 5 5
.783 .791 .667 .687 .547 .555 .0256 BSC .028 .040 100 30 20 0 -- 7 .004
19.90 20.10 16.95 17.45 13.90 14.10 .65 BSC .73 1.03 100 30 20 0 -- 7 .12
4
D D1 Datum Plane B Pin 1 Indentifier E e 0.076" (1.95mm) Ref Lead Detail E1 .13 (.005) R Min. L .20 (.008) Min. 0 Min. .13 (.30) R .005 (.012) C a
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLead Coplanarity ccc C
23
TMC22071A
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC22071AR1C TMC22071AKHC1 Temperature Range TA = 0C to 70C TA = 0C to 70C Screening Commercial Commercial Package 68-Lead PLCC 100-Lead MQFP Package Marking 22071AR1C 22071AKHC
Note: 1. 100 Lead MQFP is strongly recommended for all new board designs.
7/24/98 0.0m 002 Stock#DS7022071A

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